Random access memory (RAM) provides the temporary storage of information for today's personal computers and mainframes. As such, RAM is a necessary resource for performing computations and the amount of RAM effects the computing processing capability of any system. Each RAM component includes a number of cells or storage locations that can either hold an active or an inactive state that is referred to as a bit. A bit represents the active or inactive state with a 1 or 0, and is the smallest amount of information used by a computer.
RAM cells are combined into a large array that is used to store vast amounts of information translated binarily by computers. The RAM cells are arranged in specific groups organized in terms of Rows and Columns, with each cell having a specific Row/Column reference that is an address location.
Dynamic Random-Access Memory (DRAM) is a common form of RAM, with each DRAM cell having a capacitor and a transistor. Over time, the capacitor loses its charge, and the loss of charge results in the loss of information. It is necessary to recharge (refresh) the state in which the cell exists.
Static random access memory (SRAM) is an improved architecture over DRAM. The term “static” is derived from the fact that it does not need to be refreshed as does DRAM. SRAM requires no refresh and will maintain its information so long as it has sufficient power. This is due to the fact that internally, the SRAM cell includes flip-flop circuitry that does not require refreshing.
SRAM is also faster and more reliable than DRAM. SRAM can be used alongside the processor as cache while it performs other duties. SRAM speeds allow quicker accesses in comparison to DRAM which must wait several processor clock cycles before providing the needed information. By way of example, DRAM supports access times of about 60 nanoseconds while SRAM can support access times even lower than 10 nanoseconds. Furthermore, the SRAM cycle time is much shorter than that of DRAM, because the SRAM does not need to pause between accesses.
Unfortunately, the flip-flop circuitry may require four to six transistors that increase the size of the SRAM. The SRAM is unable to compete with the densities found in the DRAM. The density disparity substantially increases the price for SRAMs. Due to the high cost, SRAM is often used only as a memory cache.
A key concern in memory components is being able to generate smaller devices that consume less power. Although significant progress has been made in this area, a common problem with transistors is the gate voltage control of the channel as the device decreases in size. Gate voltage control is achieved by exerting a field effect on the channel. As the transistor size decreases, short-channel effects become more problematic and interfere with the gate voltage's ability to provide exclusive channel control. Ideally, total control of the channel should rest with the gate voltage.
Thus, it would be an advancement in the art to provide a SRAM cell with improved density, superior gate control, and efficient fabrication techniques. Such a device is disclosed and claimed herein.